CMOS Voltage Divider with Series Resistor

V
mA
Schematic of a CMOS voltage divider with a series resistor between PMOS and NMOS. I-V plot of the divider. Live values are reported in the status text below.
VTOP = —
VBOT = —
VR = —
IDS = —
P = —
(W/L)p = —
(W/L)n = —
Drag the dot at VBOT (left end of the bar) or VTOP (right end) horizontally to slide the bar, or vertically to change ID, clamped to the white (feasible) region. The number inputs and R slider above provide a keyboard-accessible alternative.
Process parameters: Kn′ = Kp′ = 0.2 mA/V²,   VTN = |VTP| = 0.7 V  ·  Symmetric assumption: (W/L)p = (W/L)n  ·  Slider sweeps R while holding ID constant — W/L grows to compensate