Two-NMOS Stack with Series Resistor

V
1.00 V
9.00 V
10.00 kΩ
Schematic of two NMOS transistors with a series resistor; live values are reported in the readout boxes and status text.
VTOP = —
VBOT = —
VR = —
VDS1 = —
VDS2 = —
ID = —
M1 region: —
M2 region: —
VBIAS1 sets M1 (bottom). VBIAS2 sets M2 (top). R is the resistor between VTOP (M2 source) and VBOT (M1 drain). The schematic uses voltage as the vertical axis: each node sits at y proportional to its voltage, so gates, drains, and sources all slide as you move the sliders.