Course Information
Course title: Introduction to Electronics (EE 461G)
Instructor: Dr. Daniel L. Lau · 453 F. Paul Anderson Tower · 859-257-1787 · dllau@uky.edu
Current meeting times, room and building, office hours, and the teaching assistant for this semester are posted on the course LMS (Canvas). Course Description and Prerequisites
This course introduces the analysis and design of electronic circuits using pn diodes, bipolar junction transistors (BJTs), and MOS field-effect transistors (MOSFETs), with emphasis on both large-signal and small-signal behavior and applications in analog and digital circuits. Prerequisite: EE 223 (grade C or better) and engineering standing.
Modality: In-person lectures with regular and substantive interaction through direct instruction, assessment of learning, and opportunities for student questions and discussion, consistent with AR-ASA 6.1.1.
Learning Outcomes
By the end of the course, students should be able to:
Required textbook: Fundamentals of Microelectronics, 3rd Edition, Behzad Razavi (Wiley, 2021). ISBN 978-1-119-69514-1.
Additional resources and handouts will be posted on the course LMS (Canvas) as needed. Students are responsible for regularly checking the LMS and their UK email for announcements and materials. AI Policy
The course AI policy is available here: ai_policy.pdf. LLM-generated SPICE conversation examples (created with the free versions of Perplexity, Claude, ChatGPT, and Gemini) are posted in the “LLM Spice Conversations” folder on the course LMS. Course Topics (tentative)
Exams are closed book. Students may use only an NCEES-approved calculator; no other electronic devices are permitted (including cell phones, smart watches/glasses, tablets, laptops, non-approved programmable calculators, e-readers, Bluetooth earbuds, voice recorders, cameras, or any device with wireless connectivity). Students may bring one composition-style notebook containing only handwritten notes; pages may not be added, taped, stapled, or printed. The notebook must remain intact as purchased (no loose-leaf or ring binders) and may be used on all semester exams and the final. Notebooks are collected with each exam and returned with the graded exam. An equation sheet is provided with each exam. To get ready for the exams, use the interactive practice tools below. Work each problem by hand first, then use them to check your method and find where your approach diverges from mine. As a rule of thumb, you should be scoring about 70–80% on the practice problems before sitting the corresponding exam; if you are consistently below that, keep practicing and study the worked solutions until you reach it. The practice exams with worked solutions are listed below; links will be posted as each one is finalized. Take the matching practice exam under exam-like conditions and aim to score 70–80% or better before taking the actual in-class exam.
Homework is assigned approximately weekly and mixes textbook-style analysis and design problems with SPICE circuit simulations. For all simulation problems, students submit SPICE-compatible netlist files suitable for command-line SPICE; schematic-capture / GUI tools are not required or supported. A brief written design report (a SPICE-tested circuit design, with supporting netlists) is due near the end of the term; a rubric will be provided separately. Late-work policies are specified per assignment; if unspecified, late work may not be accepted without an approved excused absence. Grading Scale and Policies
Final percentage scores combine exam scores scaled to the class maximum, homework scaled to the class maximum, and the final exam scaled to the highest score in the class, combined using the stated weights. Letter grades are assigned such that roughly the top one-fourth to one-third of the class receives an A, the next one-fourth to one-third a B, and so on; students performing significantly below their peers should expect a D or F. Requests to correct test or homework grades must be made in writing within 4 calendar days of the date the graded work is returned and must clearly state the grading error. Attendance, Communication, and Make-Up Work
Students are expected to attend all class meetings and are responsible for all material, assignments, and announcements. Email is the preferred contact outside of class and office hours, with reasonable efforts to respond within 24 hours on business days. This course follows the University policy on excused absences (AR-ASA 5.2.5.2): significant student illness (including mental health) or serious illness/death in the household or immediate family; University-related trips; major religious holidays (with advance written notice); post-graduation job or graduate-school interviews; and other causes the instructor deems reasonable. Appropriate verification may be requested. Students with an excused absence should notify the instructor within one week of the absence (or in advance for religious observances and scheduled trips) and work with the instructor to schedule make-up work. Military duties are covered under AR-ASA 5.2.5.2.3.2 via the Veterans Resource Center. No new exams or quizzes are scheduled on Prep or Reading Days, and no new homework is assigned during Finals Week. University Policies & Resources
This course uses the University’s standard academic policy statements for academic integrity, cheating and plagiarism, disability accommodations, non-discrimination and Title IX, and excused absences and make-up work, described in full on the UK Standard Academic Policy Statements page.
PDF slide decks, in course order (diodes → BJTs → MOSFETs → single-stage amplifiers → current mirrors → differential pairs).
Course title: Introduction to Electronics (EE 461G)
Instructor: Dr. Daniel L. Lau · 453 F. Paul Anderson Tower · 859-257-1787 · dllau@uky.edu
Current meeting times, room and building, office hours, and the teaching assistant for this semester are posted on the course LMS (Canvas). Course Description and Prerequisites
This course introduces the analysis and design of electronic circuits using pn diodes, bipolar junction transistors (BJTs), and MOS field-effect transistors (MOSFETs), with emphasis on both large-signal and small-signal behavior and applications in analog and digital circuits. Prerequisite: EE 223 (grade C or better) and engineering standing.
Modality: In-person lectures with regular and substantive interaction through direct instruction, assessment of learning, and opportunities for student questions and discussion, consistent with AR-ASA 6.1.1.
Learning Outcomes
By the end of the course, students should be able to:
- Understand the structures, symbols, DC characteristics, and DC models of diodes, BJTs, and MOSFETs, and perform load-line analysis.
- Analyze and design diode-based circuits such as clipping, limiting, and rectifier circuits.
- Analyze transistor circuits such as inverters and voltage followers for both analog and digital operation.
- Understand DC biasing techniques and small-signal modeling of analog circuits using BJTs and MOSFETs.
- Use SPICE-based tools to analyze and design electronic circuits.
Required textbook: Fundamentals of Microelectronics, 3rd Edition, Behzad Razavi (Wiley, 2021). ISBN 978-1-119-69514-1.
Additional resources and handouts will be posted on the course LMS (Canvas) as needed. Students are responsible for regularly checking the LMS and their UK email for announcements and materials. AI Policy
The course AI policy is available here: ai_policy.pdf. LLM-generated SPICE conversation examples (created with the free versions of Perplexity, Claude, ChatGPT, and Gemini) are posted in the “LLM Spice Conversations” folder on the course LMS. Course Topics (tentative)
- Large-signal models and analysis: pn diodes, BJTs, MOSFETs
- Small-signal models and analysis: BJTs, MOSFETs
- Digital transistor circuits: BJTs, NMOS, CMOS
- Single-transistor amplifiers: BJTs, MOSFETs
- Multiple-transistor circuits: current mirrors, active resistors, differential amplifiers
- Three semester exams: 15% each (45% total)
- Final exam: 25%
- Homework assignments: 20%
- Written design report: 10%
Exams are closed book. Students may use only an NCEES-approved calculator; no other electronic devices are permitted (including cell phones, smart watches/glasses, tablets, laptops, non-approved programmable calculators, e-readers, Bluetooth earbuds, voice recorders, cameras, or any device with wireless connectivity). Students may bring one composition-style notebook containing only handwritten notes; pages may not be added, taped, stapled, or printed. The notebook must remain intact as purchased (no loose-leaf or ring binders) and may be used on all semester exams and the final. Notebooks are collected with each exam and returned with the graded exam. An equation sheet is provided with each exam. To get ready for the exams, use the interactive practice tools below. Work each problem by hand first, then use them to check your method and find where your approach diverges from mine. As a rule of thumb, you should be scoring about 70–80% on the practice problems before sitting the corresponding exam; if you are consistently below that, keep practicing and study the worked solutions until you reach it. The practice exams with worked solutions are listed below; links will be posted as each one is finalized. Take the matching practice exam under exam-like conditions and aim to score 70–80% or better before taking the actual in-class exam.
- Practice Exam 1 — Diode Circuit Analysis: two interactive web pages for studying — the Diode / Zener Transfer-Function Quiz (a randomly generated multiple-choice drill on the transfer characteristics of diode and Zener circuits—the shape of Vout or Iout vs Vin, a slope, or a turn-on voltage; every circuit is validated against ngspice, with worked answers and transfer-function plots) and the interactive practice exam with worked solutions and SPICE-verified plots, plus a built-in calculator.
- Practice Exam 2 — Transistor (BJT & MOSFET) Circuit Analysis: interactive practice exam with worked solutions and SPICE-verified plots, plus a built-in calculator.
- Practice Exam 3 — Current Mirrors & Differential Amplifiers: interactive practice exam with worked solutions, plus a built-in calculator.
- Practice Final Exam: coming soon — link to be posted.
Homework is assigned approximately weekly and mixes textbook-style analysis and design problems with SPICE circuit simulations. For all simulation problems, students submit SPICE-compatible netlist files suitable for command-line SPICE; schematic-capture / GUI tools are not required or supported. A brief written design report (a SPICE-tested circuit design, with supporting netlists) is due near the end of the term; a rubric will be provided separately. Late-work policies are specified per assignment; if unspecified, late work may not be accepted without an approved excused absence. Grading Scale and Policies
Final percentage scores combine exam scores scaled to the class maximum, homework scaled to the class maximum, and the final exam scaled to the highest score in the class, combined using the stated weights. Letter grades are assigned such that roughly the top one-fourth to one-third of the class receives an A, the next one-fourth to one-third a B, and so on; students performing significantly below their peers should expect a D or F. Requests to correct test or homework grades must be made in writing within 4 calendar days of the date the graded work is returned and must clearly state the grading error. Attendance, Communication, and Make-Up Work
Students are expected to attend all class meetings and are responsible for all material, assignments, and announcements. Email is the preferred contact outside of class and office hours, with reasonable efforts to respond within 24 hours on business days. This course follows the University policy on excused absences (AR-ASA 5.2.5.2): significant student illness (including mental health) or serious illness/death in the household or immediate family; University-related trips; major religious holidays (with advance written notice); post-graduation job or graduate-school interviews; and other causes the instructor deems reasonable. Appropriate verification may be requested. Students with an excused absence should notify the instructor within one week of the absence (or in advance for religious observances and scheduled trips) and work with the instructor to schedule make-up work. Military duties are covered under AR-ASA 5.2.5.2.3.2 via the Veterans Resource Center. No new exams or quizzes are scheduled on Prep or Reading Days, and no new homework is assigned during Finals Week. University Policies & Resources
This course uses the University’s standard academic policy statements for academic integrity, cheating and plagiarism, disability accommodations, non-discrimination and Title IX, and excused absences and make-up work, described in full on the UK Standard Academic Policy Statements page.
- Academic integrity: Students must uphold the highest standards of academic integrity in all exams, assignments, simulations, and reports; suspected violations are addressed under University regulations.
- Disability accommodations: Provide a Letter of Accommodation from the Disability Resource Center (DRC) (Multidisciplinary Science Building, Suite 407; 859-257-2754; drc@uky.edu). Accommodations are not retroactive—contact the DRC early.
- Non-discrimination & Title IX: UK is committed to a learning environment free of discrimination, harassment, and sexual misconduct (ARs 6:1 and 6:2). See the Office of Institutional Equity and Equal Opportunity (13 Main Building; 859-257-8927).
- Emergencies: Dial 911, or UK Police at 859-257-8573 (#UKPD from a mobile). Enable UK Alert, use the LiveSafe app, and follow run–hide–fight guidance and the instructor’s directions.
PDF slide decks, in course order (diodes → BJTs → MOSFETs → single-stage amplifiers → current mirrors → differential pairs).
- Lecture 1 — Circuit Analysis Review
In this opening lecture, I review the circuit-analysis techniques the rest of the course depends on. We work through a representative resistive circuit, reduce it to its Thévenin equivalent, and solve it with nodal and mesh analysis. I then introduce the idea of a small-signal model—linearizing a circuit about its operating point—which becomes our central tool for analyzing amplifiers. The aim is to make sure everyone is comfortable separating a circuit's large-signal (DC bias) behavior from its small-signal (AC) behavior before we add nonlinear devices. After this lecture, you should be able to reduce a resistive network to its Thévenin equivalent, solve a circuit by nodal and mesh analysis, and identify the operating point about which a small-signal model is formed. - Lecture 2 — Diode Models
Here I introduce the pn-junction diode, beginning with its physics, the exponential current–voltage (Shockley) relationship, and the role of the thermal voltage. Because the exponential is awkward to solve by hand, I develop the three piecewise-linear models we use all semester: the ideal diode, the constant-voltage-drop model, and the constant-voltage-drop-plus-resistance model. I show how to derive each model's parameters from the diode equation and then analyze the same circuit with each model, including the guess-and-check (proof-by-contradiction) method for deciding whether a diode is on or off. We finish by comparing the three models against a SPICE simulation so you can see how much accuracy each one buys you. After this lecture, you should be able to write down the three piecewise-linear diode models, derive their parameters from the diode equation, use the guess-and-check method to decide whether a diode is on or off, and analyze a single-diode circuit with each model. - Lecture 3 — Diode as a Transfer Function & Half-Wave Rectifier
In this lecture, I reframe the diode as an input–output transfer function and use that view to analyze a family of practical circuits: the half-wave rectifier, one-sided and bidirectional clippers and limiters, and the Zener diode as a voltage reference. I also show how placing diodes in parallel reduces the forward-voltage loss. To connect the hand analysis to simulation, I include an interactive in-browser tutorial, Piecewise-Linear Diode Models in SPICE, where you step through how each PWL model is written as a SPICE netlist and watch the resulting transfer characteristic—including the Zener breakdown region—so you can check your hand calculations against the simulator. After this lecture, you should be able to sketch the transfer characteristic of a diode circuit, analyze half-wave rectifiers, clippers, and limiters, recognize a Zener voltage reference, and write a piecewise-linear diode model as a SPICE netlist. - Lecture 4 — Half-Wave Rectifier with Capacitor Filter
Building on the previous lecture, I add a filter capacitor to the half-wave rectifier to turn its pulsating output into a usable DC supply. We analyze the charge-and-discharge operation, derive the ripple voltage, and see how the load resistance, capacitor size, and source frequency trade off against ripple. I also work the case of two diodes in series and then extend the discussion from half-wave to full-wave rectification, which halves the ripple for the same components. After this lecture, you should be able to analyze a half-wave rectifier with a filter capacitor, estimate its ripple voltage, choose the capacitor and load values for a target ripple, and explain the advantage of full-wave over half-wave rectification. - Lecture 5 — Diode Circuit Analysis (Practice Exam Solutions)
These slides contain my fully worked solutions to a practice Exam 1 on diode circuit analysis. Each problem is solved step by step using the diode models, rectifiers, and limiter circuits from the diode lectures, with the reasoning shown in full. I recommend attempting each problem on your own first and then using these solutions to check your method and find where your approach diverges from mine. After this lecture, you should be able to solve exam-level diode circuit problems efficiently, selecting the appropriate diode model and verifying your on/off assumptions. - Lecture 7 — Bipolar Junction Transistor (BJT) Physics
Here I introduce the bipolar junction transistor. I start with the device physics and the collector (output) characteristics, then build the common-emitter amplifier and identify its operating regions on the load line. I introduce transconductance as the key small-signal parameter linking input voltage to output current, and develop the BJT small-signal model that we use for all of the amplifier analysis that follows. After this lecture, you should be able to read a BJT's output characteristics, identify its operating region from the terminal voltages, draw the load line of a common-emitter stage, and write the BJT small-signal model with its transconductance. - Lecture 8 — BJT Amplifier Biasing & Q-Point Design
In this lecture, I focus on biasing—choosing the DC operating point (Q-point) of a common-emitter amplifier so that it amplifies without clipping. We design the Q-point, examine what happens at the edge of saturation, and study how the collector resistor sets the gain and the available output swing. From there I build up more realistic configurations: parallel CE amplifiers, adding a base resistor, the diode-connected BJT, and finally the active load, which previews how we replace bulky resistors with transistors. After this lecture, you should be able to design the Q-point of a common-emitter amplifier, test whether it sits at the edge of saturation, predict how the collector resistor affects gain and output swing, and replace a load resistor with a diode-connected or active load. - Lecture 9 — MOSFET Physics
This is the MOSFET counterpart to the BJT lecture. I cover MOSFET device physics and output characteristics, build the common-source amplifier, and locate its operating regions on the load line. I again introduce transconductance and the small-signal model, drawing out the parallels and the differences with the BJT. To make the large-signal behavior concrete, I include an interactive demo, a common-source amplifier load-line and VTC tracer, that lets you drag the bias and component values and watch the load line move and the voltage transfer characteristic redraw in real time, so you can see exactly where the amplifier enters and leaves saturation. After this lecture, you should be able to read a MOSFET's output characteristics, identify its operating region, draw the common-source load line, and write the MOSFET small-signal model with its transconductance. - Lecture 10 — MOSFET Amplifier Biasing & Q-Point Design
Here I design the bias point of the common-source amplifier in detail—placing the Q-point, identifying the edge of triode, and analyzing how the drain resistor sets the gain and the output swing. I then build toward more practical circuits with parallel amplifiers, a gate resistor, and the diode-connected (gate-drain-connected) MOSFET. The accompanying interactive demo, a resistor-load CS amplifier load-line and VTC tracer, lets you change the drain resistor and bias point and watch the operating point and transfer characteristic respond, which makes the trade-off between gain and headroom tangible. After this lecture, you should be able to design the Q-point of a common-source amplifier, locate the edge of triode, predict how the drain resistor sets gain and swing, and analyze a diode-connected MOSFET. - Lecture 11 — Common-Emitter / Common-Source Amplifier with Active Load
In this lecture, I replace the resistor load with an active (transistor) load in both the common-emitter and common-source amplifiers and carry out the small-signal analysis, showing why an active load delivers far more gain than a practical resistor. I also introduce two important buffer stages: the common-collector amplifier (emitter follower) and its MOSFET equivalent, the source follower (common drain), which provide near-unity voltage gain with low output impedance. After this lecture, you should be able to analyze a common-emitter or common-source amplifier with an active load, explain why it gives more gain than a resistor load, and find the gain of an emitter follower or source follower. - Lecture 12 — The Common-Emitter Amplifier
This lecture gives a complete, side-by-side treatment of the common-emitter (BJT) and common-source (MOSFET) amplifiers. For each, I work the large-signal (DC bias) analysis and then the small-signal (AC gain) analysis, and I cast the result as a two-port network model so the stage can be dropped into a larger system. I compare the BJT and MOSFET versions directly and verify the hand analysis with SPICE. After this lecture, you should be able to carry out the DC bias and AC small-signal analysis of a common-emitter or common-source amplifier, represent it as a two-port model, and verify your gain in SPICE. - Lecture 13 — Common-Collector (Emitter-Follower) Bias Circuit
This is a short, fully worked example in which I bias a common-collector (emitter-follower) circuit and find its DC operating point. It serves as a focused, concrete walk-through of the follower's biasing before we use it as a buffer stage in larger circuits. After this lecture, you should be able to bias a common-collector (emitter-follower) circuit and find its DC operating point. - Lecture 14 — Common-Source Amplifier with Resistor Load
Here I compare three different loads for the common-source amplifier—a passive resistor load, an NMOS active load, and the CMOS inverter—and show what each does to the gain and the output swing. I carry out the small-signal analysis of the CMOS case and finish with a direct comparison of all three, which motivates why integrated circuits favor active loads over resistors. After this lecture, you should be able to compare resistor, active-load, and CMOS-inverter loads for a common-source amplifier, analyze the small-signal gain of a CMOS stage, and explain why active loads are preferred in integrated circuits. - Lecture 15 — CE Small-Signal Model (Review)
In this lecture, I review the common-emitter small-signal model and then introduce the test-source method—applying a test voltage or current and measuring the response—as a systematic way to find a circuit's input and output impedance. This technique becomes essential once the circuits grow complex enough that inspection no longer works. After this lecture, you should be able to apply the test-source method to find the input and output impedance of an amplifier and simplify a small-signal circuit systematically. - Lecture 16 — NMOS–NMOS Voltage Divider
Here I analyze voltage dividers built from transistors instead of resistors: the NMOS–NMOS divider and the PMOS–NMOS (CMOS) divider, working out the operating point in each case. These dividers lead naturally into the NMOS current mirror, which I introduce at the end. To build intuition, I include three interactive demos—a two-NMOS stack with a series resistor, a CMOS voltage divider made from diode-connected PMOS and NMOS devices, and the same CMOS divider with an added series resistor. In each, you adjust the device sizes and the resistor value and watch the node voltages and branch current settle, which shows how the transistors share the supply and set the bias current. After this lecture, you should be able to find the operating point of an NMOS–NMOS or PMOS–NMOS voltage divider and explain how it forms the basis of a current mirror. - Lecture 17 — NMOS Current Mirror
In this lecture, I develop the current mirror in depth. Starting from the single NMOS mirror, I extend it to multiple mirrored outputs, then build the PMOS current mirror and give the intuition for how it sources current from the top of the circuit. I close with a SPICE study of how large the load resistance can grow before the mirror transistor falls out of saturation and the mirror stops working. After this lecture, you should be able to design an NMOS or PMOS current mirror, set up multiple mirrored outputs, and determine the maximum load resistance before the mirror leaves saturation. - Lecture 18 — NMOS with Current-Source Biasing
Here I bias an NMOS transistor with a current source rather than a resistor. We find the source and drain voltages, verify that the device stays in saturation, and determine the maximum allowable bias voltage. I then connect this to a practical MOSFET current-mirror implementation and use it to introduce the differential pair, the workhorse input stage of analog circuits. After this lecture, you should be able to bias a MOSFET with a current source, find its terminal voltages, verify saturation, determine the maximum bias voltage, and recognize the structure of a differential pair. - Lecture 19 — Common-Mode & Differential Voltages
In this lecture, I define common-mode and differential-mode voltages and apply them to the differential pair, showing how it amplifies the difference between its two inputs while rejecting what they have in common. I carry out the BJT differential-pair analysis and verify the behavior with SPICE. After this lecture, you should be able to decompose a pair of inputs into common-mode and differential components and analyze the differential gain of a BJT differential pair. - Lecture 20 — Replacing the Drain Resistor with a Current Mirror
Here I motivate replacing the differential pair's drain (or collector) resistors with a current-mirror active load, which converts the differential output to a single-ended one and dramatically raises the gain. I analyze both the MOSFET and BJT differential pairs with this active load. After this lecture, you should be able to analyze a differential pair with a current-mirror active load and explain how it converts a differential signal to single-ended while increasing the gain. - Lecture 21 — Basic Current Mirror and Cascode
In this lecture, I review the basic current mirror and then develop the cascode current mirror for both NMOS and BJT implementations. We analyze the much higher output resistance the cascode provides, weigh it against the reduced voltage headroom, and compare the basic and cascode mirrors side by side. After this lecture, you should be able to design a cascode current mirror, compute its output resistance, and weigh its headroom cost against a basic mirror. - Lecture 22 — BJT Differential Pair (Student Questions)
This lecture is organized around the questions students most often ask about the BJT differential pair. I address why the tail current source appears the way it does in the small-signal circuit, why the shared emitter node behaves as a virtual ground for differential signals, and what the analysis is ultimately trying to find. I close by setting up the homework circuit—a MOSFET differential pair with an active load. After this lecture, you should be able to explain the role of the tail current source in the small-signal model, justify the virtual ground at the shared emitter node, and set up the analysis of a MOSFET differential pair with an active load. - Lecture 23 — BJT Differential Pair with Single-PNP Active Load
In this final lecture, I work a complete SPICE-based example of a BJT differential pair with a single-PNP active load. I build the netlist from the schematic, find the DC operating point, run the simulation, and interpret the results, tying together the differential-pair and current-mirror ideas from the preceding lectures. After this lecture, you should be able to write the SPICE netlist for a BJT differential pair with an active load, find its DC operating point, and interpret the simulation results.
